ISEL=0, BIGEND=0, CURPIPE=0x0, RCNT=0, REW=0, MBW=0
CFIFO Port Select Register
| CURPIPE | CFIFO Port Access Pipe Specification 0 (Others): Setting prohibited 0 (0x0): Default Control Pipe 1 (0x1): Pipe 1 2 (0x2): Pipe 2 3 (0x3): Pipe 3 4 (0x4): Pipe 4 5 (0x5): Pipe 5 6 (0x6): Pipe 6 7 (0x7): Pipe 7 8 (0x8): Pipe 8 9 (0x9): Pipe 9 |
| ISEL | CFIFO Port Access Direction When DCP Is Selected 0 (0): Select reading from the FIFO buffer 1 (1): Select writing to the FIFO buffer |
| BIGEND | CFIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | CFIFO Port Access Bit Width 0 (0): 8-bit width 1 (1): 16-bit width |
| REW | Buffer Pointer Rewind 0 (0): Do not rewind buffer pointer 1 (1): Rewind buffer pointer |
| RCNT | Read Count Mode 0 (0): The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0], D0FIFOCTR.DTLN[8:0], D1FIFOCTR.DTLN[8:0]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN[8:0] value is cleared when all data is read from only a single plane. 1 (1): The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. |